India formally joined the Pax Silica grouping on February 20. India is deeply embedded in the design segment of the semiconductor supply chain, and hence India’s presence in the grouping was anticipated. This membership will help Indian firms gain access to important markets and ease the flow of inputs such as chips, chip-making software, and manufacturing equipment. With this positive development, the sole determinant of India’s success is the rate of implementation of semiconductor policy initiatives back home.
The latest Union budget identified semiconductors as one of the seven strategic and frontier sectors in which the government wants to strengthen India’s manufacturing presence. To realize this vision, the budget speech mentioned a plan to launch a second version of the India Semiconductor Mission (ISM) that will “produce equipment and materials, design full-stack Indian IP, and fortify supply chains”.
As four years have passed since the launch of ISM1.0, this is a good time to assess progress using the government’s own spending data over the past four budgets. To make a fair assessment, one must go beyond speeches and announcements to examine actual budget allocations and disbursements.
Every financial year has two relevant numbers: The budgeted estimate at the start of the year and the actual disbursements by the end of the year. If the difference is large, it indicates that the project is not going as planned. If the difference is small or negative, it indicates that the spending matches government expectations.
This difference matters all the more for ISM1.0 because spending under these schemes is supposed to occur on an equal footing with firms during the capital acquisition and construction stages. This is unlike Production-linked Incentives (PLI), where financial support is contingent on production. Thus, a large difference between budgeted estimates and actual spending directly suggests slower-than-expected progress. In FY27, the government expects to spend approximately ₹8,000 crore — roughly 10% of the total outlay — for projects already approved under ISM 1.0. Breaking down this overall number reveals the health of each of the five sub-schemes.
The scheme proceeding well is the one for assembly and specialized fabs. While a gap persists between budgeted estimates and disbursals, the steady rise in disbursements in absolute terms indicates genuine on-ground progress. Micron’s facility in Gujarat is ramping up, CG Power’s OSAT plant in Sanand has begun pilot production, and a total of nine projects are under construction. This segment represents the most tangible success of India’s semiconductor push.
The budgeted outlay for fab construction presents a more muted picture. Despite allocations for the Tata-PSMC Dholera fab in FY24 and FY25, not a single rupee was disbursed in those years. The FY26 revised estimate is also substantially lower than the budgeted allocation, indicating that the project is progressing more slowly than the government’s own projections suggested. India’s sole CMOS fabrication unit remains critical to semiconductor ambitions, but timelines clearly need recalibration.
The government has also been planning to modernize the state-owned research and development fabrication unit at SCL Mohali for several years, with little success. Despite allocating money in multiple budgets, virtually nothing has been spent. In November 2025, a grand ₹A 4,500-crore modernization plan was announced, with promises to upgrade the facility to 180nm capability and increase wafer production 100-fold. Yet, the pattern of ambitious announcements followed by tepid execution persists.
However, the performance in fabless chip design, a sector where India comparatively has advantage, is disappointing. The Design-Linked Incentive scheme promised to support 100 start-ups in their go-to-market strategy, but disbursals reveal how far off target it remains. There was no disbursement in FY23; FY24 disbursements stood at 15% of the budgeted ₹200 crores; FY25 disbursements reached only 34% of the budget; and FY26 managed 52%. For FY27, the budgeted expenditure stands at ₹100 crores.
The reasons for this chronic underperformance include strict provisions that disqualify firms, which raise substantial foreign capital, confusion over the government’s rights to a company’s intellectual property, and the decision to entrust a government company — which is itself a player in this domain — as the nodal regulator. Hopefully, ISM2.0 will resolve some of these constraints.
The display fab scheme has attracted no interest whatsoever, and the government has not budgeted any amount for it this year. Display fabs are not strategically critical, and spending taxpayer money on them merely to reduce imports from China is not sensible. If the government has finally decided to abandon this scheme, it would be a welcome instance of policy pragmatism. Letting private players build display fabs on their own dime if they see commercial merit is a better strategy.
The headline announcement is India Semiconductor Mission 2.0, which aims to move beyond fab construction to focus on semiconductor equipment, materials, and full-stack Indian IP development. A budget of ₹₹1,000 crore has been allocated for FY27, indicating a gradual ramp-up.
Finally, a related scheme is the Electronics Components Manufacturing Scheme, which is meant to incentivize the production of electronics components apart from chips, such as resistors and multi-layered printed circuit boards. Finance minister Nirmal Sitharaman cited high demand for this programme, and raised its outlay to ₹40,000 crore from ₹22,000 crore, of which ₹1,500 crore is for the next financial year.
In sum, India’s semiconductor journey remains a work in progress. The assembly segment shows genuine momentum, but fab construction appears to be behind schedule. SCL Mohali modernization remains more promising than reality, and the design ecosystem — where India has natural strengths — needs better incentives. The focus of ISM 2.0 on equipment and materials is strategically sensible, but execution will be key. With Pax Silica membership in place, the semiconductor mission needs less rhetoric and more implementation.
Pranay Kotasthane, co-author of When the Chips are Down, a book on semiconductor geopolitics, is the deputy director at the Takshashila Institution. The views expressed are personal
